One aspect of integrated circuit design that is critical for circuit performance is the timing of the circuit elements, interconnects, and nets within the circuit. As very large scale integrated circuit (VLSI) fabrication technology reaches submicron device dimensions and circuit speed falls into the sub-nanosecond range, timing delays become more and more important as factors in determining circuit speed and performance.
Currently, the design of electronic circuits and systems employs computer-automated design systems (also known as electronic design automation or EDA tools) for defining and verifying various circuit configurations. Typically, circuit definition is accomplished by graphically entering circuit schematics at an engineering workstation or by using a logic synthesis tool, which generates a high-level, hardware description file functionally describing the logic of the desired prototype circuit. As part of the circuit definition, a number of delay constraints are specified by the circuit designer. These delay constraints must be satisfied when the circuit is designed and fabricated.
A computer-aided timing analysis tool can be used to estimate propagation delays through each net or a section of a net in a signal path. When an unacceptable delay is identified, optimization may be performed to correct the timing delay problems. For example, timing optimizations in a circuit may be performed by modifying a critical net to include additional buffers, repeaters, or by resizing gates within the net to address a timing problem.
As the quantity of data in modern integrated circuit (IC) designs become larger and larger over time, the execution time required to process EDA tools upon these IC designs also becomes greater. With respect to the process of performing timing analysis and optimization, the more circuit elements that are on an IC design, the greater amounts of time and resources that are needed that are normally needed to identify and correct the timing problems. This problem is exacerbated by constantly improving IC manufacturing technologies that can create IC chips at ever-smaller feature sizes, which allows increasingly greater quantities of circuit elements to be placed within the same chip area which may cause greater numbers of timing problems.
To achieve faster and more efficient results, it is therefore desirable to perform EDA processing upon an IC layout without having to consider the entirety of the circuit design. Instead, it is desirable to be able to analyze and optimize discrete portions of the circuit design.
A typical approach to solve large analysis problems is with a divide and conquers approach, such as partitioning or hierarchical approaches. The partitioning or hierarchical analysis approaches divide a large circuit design into smaller manageable portions, and then separately analyzes and optimizes these circuit portions. The partitioning approach essentially breaks the design into a set of discrete partitions. The hierarchical approach divides a flat circuit design into separate portions based upon hierarchical partitioning.
The problem is that the partitioning approaches taken by existing EDA tools/techniques may negatively affect timing if certain areas of the design external to the partitions are not considered for the optimization. For example, if the optimization only considers a given portion of the design, i.e., certain partitions, and those portions affect or are affected by other portions of the design, then optimization taken in isolation may cause unintended effects upon the timing both within the analyzed/optimized partitions as well as in the not-considered partitions.
This type of problem could cause extra iterations to be performed in the design/timing process to correct the unintended problems. This in turn can significantly affect the designer in the processing of the design cycle both financially and in terms of product timing and release.
Therefore, there is a need for an improved approach for handling partitions that addresses external portions of the overall design that would be affected by processing and optimization of the contents of the partitions.